Thesis Defense: Effective and Flexible Acceleration of Sparse Computations

Abstract: Sparsity is ubiquitous and abundant in many important application domains including deep neural networks (DNNs), big data analytics and scientific computing. Leveraging sparsity in these applications is a promising way to gain more efficiency in performance, energy and resource utilization when designing hardware accelerators. However, exploiting sparsity in hardware accelerators both effectively and flexibly is challenging. First, sparse computations often involve data with a wide range of sparsity ratios. Second, sparse computation demands a wide range of sparse data representations. And supporting the wide range of sparsity ratio and data representation efficiently in hardware is challenging. Third, the choice of sparse data representations limits the choice of efficient dataflows (compute schedules). Finally, sparsity causes dynamism which manifests as large variations of work and variable access latencies.

To address these challenges, this thesis proposes codesigning data representation, dataflow, and hardware architecture to exploit sparsity effectively and flexibly. Leveraging this codesign approach, we propose three architectural techniques to accelerate important sparse applications including graph analytics, linear algebra and DNNs. SpZip is an architectural technique that accelerates a wide range of sparse data traversal and exploits data compression to address the data movement bottleneck of graph analytics and sparse linear algebra. ISOSceles is a hardware accelerator that dramatically reduces data movement of sparse CNN through inter-layer pipelining (fine-grain layer fusion). Trapezoid is a unified architecture that accelerates matrix multiplication effectively with a wide range of input sparsity ratio. All three designs achieve significant performance improvements over state-of-the-art accelerators for sparse computations.

Zoom link: https://mit.zoom.us/j/97088952009